(Solved): Verilog HDL - Gate level Modelling for the following specification 1. Design a logic circuit to si ...

Verilog HDL - Gate level Modelling for the following specification 1. Design a logic circuit to simulate the prime number detector from \( (0-15) \). 2. Design a 4 bit code converter to convert from 4 bit binary to \( \left(\begin{array}{lll}8 & 4 & -2\end{array}\right) \) code using minimum number of logic gates.