(Solved): The adder tree below is used to compute the sum of eight inputs on every clock cycle, where the su ...

The adder tree below is used to compute the sum of eight inputs on every clock cycle, where the sum is: \( S=R+T+U+V+W+X+Y+Z \). Assume the propagation delay through one adder is \( 3 \mathrm{~ns} \). Consider a pipelined version of the adder tree, with a pipeline register at the output of each of the first two levels of the adder tree, to maximize the clock speed at which we can operate the circuit. Compare the fastest latency and throughput values for the original circuit versus the pipelined circuit, where throughput \( =1 \) output/ ns. (Hint: See definitions of latency and throughput on p. 379 of the textbook). Please neglect sequential delay through registers and setup time on registers. Enter answer in integer format only. For the origin circuit, latency \( =\quad \) ns, throughput \( =1 \) output/ ns. For the pipelined circuit, latency \( =\quad \) ns, throughput \( =1 \) output/ ns.