Q5. Cache Coherence [20 points]
a. (6p) Why do we need a cache coherence protocol? Explain it?
b. (7p) For a directory based cache coherence protocol, there are 4 processors and following requests arrive for a specific cache block. Show the directory entry after each request.
P1 takes a read miss
P2 takes a write miss
P3 takes a read miss
P4 takes a read miss
P1 takes a read miss
P2 takes a write miss
c. (7p) Compare MESI and MSI protocols. What are their differences and what was the problem that MESI is fixing?