(Solved): Part 2, Using Gate level style only, SystemVerilog 7 In Lab Part 1: Designing the Base Module T ...

Part 2, Using Gate level style only, SystemVerilog

7 In Lab Part 1: Designing the Base Module The base of a 3 to 8 decoder is a collection of smaller modules. This uses Shannon's Expansion Theory to combine 2 to 4 decoders and 1 to 2 decoders. To accomplish this, the smallest module needs to be properly functioning before the other modules can be created. Create the properly commented 1 to 2 decoder using only the gate level style. Name the module decoder1to2. The 1 to 2 decoder follows the following truth table: Table 1: Table for Part 1 Create the standard set of simulation and synthesis elements to test your design. Include these on the data sheet and make sure they are saved to be used in the report. Yosys has more ways to synthesize, take a look at what happens with another approach. Change the setting to "use $$ABC$$ with cell library" and run again. Take a screenshot and add it to your sheet for the lab, and to be included in the report. Download the results.zip file and rename it. "lastname" is your last name. If you work with a partner on it during lab, name it: lastname_lastname_lab6_1_to_2_dec.zip Otherwise name it: lastname_lab6_1_to_2_dec.zip This will be submitted with the final submission. 8 Part 2: 2 to 4 Module Extension The creation of a 2 to 4 decoder leveraging Shannon's Expansion Theory using modular design and gate level styling requires instantiation of the decoder 1 to2 module. According to Shannon's Expansion Theory, we can factor out a variable and evaluate for each case of that variable with the remaining system elements. $$F(A,B,C,D)=A{}^{?}F(B,C,D)+A^{??}F(B,C,D)$$ In terms of the system as a modular MSI design, this means the 1 to 2 decoder is used 2 times and the result anded with the input not used for the 2 to 1 decoder. Create the module to implement the 2 to 4 decoder with the name decoder2to4. Use the gate level style, this restricts the elements that can be used to the primitive gates and the custom module created in Part 1. Synthesize the module created in this part. It will give you an error message the first time through. That is expected. This happens because of the limitation of abstraction capabilities with Yosys. Comment out the module that is instantiated and then synthesize again. Take a screenshot of the synthesized design and add it to the document created in Part 1. For testing purposes (due to the extent of coverage in lecture that may have happened in lecture), here is the truth table for the module to help with the test cases placed in the testbench. Table 2: Table for Part 2 Simulate the system to create the wave and log, include the screenshots in your data sheet and for the report. Download the results.zip file and rename it. "lastname" is your last name. If you work with a partner on it during lab, name it: lastname_lastname_lab6_2_to_4_dec.zip Otherwise name it: lastname_lab6_2_to_4_dec.zip This will be submitted with the final submission.