(Solved): Logic Circuits Using Quartus II and Reduction Techniques Objective: This lab is about building log ...

Logic Circuits Using Quartus II and Reduction Techniques Objective: This lab is about building logic circuits using Quartus II software. Finding the truth table of the logic circuit manually and by the timing diagram of Quartus II software. Finally, reduction techniques will be applied to minimize the logic circuits. Logic Equation: \( Y=A B+(B C)^{\prime} \) Task-1: Draw the logic circuit diagram of the above equation and write down the truth table. Task-2: Use Quartus II to implement the logic circuit using block diagram and show the timing diagram. Compare timing diagram with your truth table. Question: (i) Reduce the logic equation either by using Karnaugh map or by using laws and rules of Boolean algebra. [Hint: if using laws and rules of Boolean algebra, use De Morgan's Law and rules number 10\( ] \) (ii) After minimizing the logic equation [from question (i)], redraw the logic circuit using AND, OR, NOT logic gates. (iii) Is it possible to implement the circuit using VHDL code? If yes, which library you need to include? Next few pages show how to use block diagram and timing diagram of Quartus II software.