(Solved): In VHDL code only please Coding, simulation and synthesis assignment Write a VHDL program to synt ...

In VHDL code only please

Coding, simulation and synthesis assignment Write a VHDL program to synthesize the register of size $$\mathbf{n}$$ shown below. The inputs are data in, enable and clock. The output is data_out. The data_in and data_out busses have $$\mathrm{n}$$ bits each. The register stores the data present in the data in bus on the positive-edge of the clock regardless of the value of enable. The purpose of the enable signal is to enable placing the contents of the register onto the data_out bus; therefore, you will expect tri-state buffers at the outputs of the register. It should function as follows: when enable = ' 1 ' the data stored in the register is placed onto the data_out bus when enable = ' 0 ' data_out is at high impedance (Z); therefore the register is disconnected from the bus If you try writing the code with one process you will soon find that it is very clumsy and/or it might not result in the hardware you want. The nicer solution is to split the code in the architecture into 2 sections, one to synthesize the flip-flops (due to a clock event) and the other section to synthesize the combination logic (i.e., the tri-state buffers). You will do this in two different ways. Write 2 programs as follows: Program \#1: Use two processes that communicate with each other via a signal that you declare in the architecture. For purposes of this explanation, let's call that signal internal_data. You can also have the two processes communicate with each other via a shared variable (see page 179 in the textbook). In one process, internal_data gets data_in when a positive clock edge happens. This process should generate $$\mathbf{n}$$ flip-flops. You will have to use generic in your entity. The second process should be a non-registered process (only combination logic should result from it) to create the tri-state buffers. The second process is sensitive to changes in enable and internal_data. When either changes you check the value of enable and accordingly either place the contents of the register (internal_data) onto the data_out bus or you disconnect the register from the data_out bus : data_out <= (others => ' $$Z$$ '); Program \#2: Make a copy of program 1 to create program 2. Replace the second process by a combinational statement (WHEN ELSE or WITH/SELECT/WHEN) to create the tri-state buffers.