(Solved): Design clock with Alarm project using Quartus 13.1. A) Implements a clock with Alarm that displays ...

Design clock with Alarm project using Quartus 13.1. A) Implements a clock with Alarm that displays the hours, minutes and seconds on 7-segment displays of the FPGA. The user may have the ability to change the display format from 24 hour to 12 hour format and vice versa by using a switch. Moreover, the initialization of the time for the clock can be done by the user by using push buttons otherwise it should start on 000000 on 12 hour format or 235959 on 24 hour format (figure below). B) Add an alarm clock functionality, Let all the LEDs lighting when reach the time. Project Deliverable (Week 16): You must submit a report along with your circuit (showing your design in details). You need to upload the whole Quartus project folder along with the report. The report must be typed. The report must contain the following information: - Verilog HDL code for the "clock" module [20\% points] - Design the test bench for the "clock" module [5\% points] - Verilog HDL code for the "alarm clock" module [20\% points] - Design the test bench for the "alarm clock" module [5\% points] - Write the Verilog HDL code for the 7-segment Display. [10\% points] - Create a symbol for your "clock" module. [5\% points] - Create a symbol for your 7-segment display. [5\% points] - Design the block diagram to implement the whole project as per Figure 1 above. [7.5\% points] - Verify the design by showing the simulation results using vector waveform file (. vwf). [7.5\% points] - Pin Assignments as per Altera FPGA that you are using in your lab [7.5\% points] - Report format. [ \( 7.5 \% \) pointS].