(Solved): Consider an FPGA with 50IO pads. Each of these IO pads can be configured as input/output/inout, an ...

Consider an FPGA with $50\mathrm{IO}$ pads. Each of these IO pads can be configured as input/output/inout, and the total number of combinations of configurations for each IO pad is 13. The FPGA consists of 250,000 4-input LUTs. The switchboxes in the FPGA contain 25 wires in the horizontal direction, and 30 wires in the vertical direction. I use this FPGA to implement my radar signal processing algorithm. The radar processor needs 32 input pins for data, 12 output pins for the result and 6 inout pins for control information. It uses $65\%$ of the LUTs and $79\%$ of the switchboxes. A) Can you suggest a reason why the switchboxes contain more wires in the vertical direction than in the horizontal direction? B) What is the size of the bitstream for this FPGA? C) What fraction of the bits in the bitstream for my radar signal processing algorithm are unspecified (don't care)? D) How many distinct bitstreams can I construct, each of which implement the radar signal processing algorithm?