Consider a circuit with one input X and one output Z. The circuit should output Z=1 if and only if exactly two 1’s, followed by a 0, followed by a 1 are detected at the input X. In other words, the circuit should detect the pattern “1101” when the pattern has been preceded by a 0. The following timing trace depicts the expected behavior for the circuit. Detected patterns are underlined. One pattern of 1101 which should not be detected is shown in a rectangle; this pattern is not detected because it is preceded by a leading 1.
(6 pts) Design a synchronous circuit for this problem using D Flip-Flops. Show all your work