(Solved): [Carry-lookahead adder] An n-bit adder can be constructed by cascading n full adders in series, with ...

[Carry-lookahead adder] An n-bit adder can be constructed by cascading n full adders in series, with the carry into stage i, C_i, coming from the output stage i – 1. The carry into stage 0, C₀, is 0.

However, gate has propagation delay. If each stage takes T nsec to produce its sum and carry, the carry into stage iwill not be valid until iT nsec after the start of addition. For large n the time required to carry to ripple through to the high-order stage may be unacceptable long.

Design a 4-bit adder that works faster. I.e. Figure out the digital circuit of the gray part of the diagram below. PLEASE DRAW IT!

Hint:

For a 1-bit full adder, if A, B are both 1, then the carry-out is certainly 1.

If A+B (arithmetic addition) is 1, and the carry-in is 1, then the carry-out is 1.

I.e. if A?B (logical XOR) is 1, and the carry-in is 1, then the carry-out is 1.

So the carry-out can be written as

C_out = AB + (A?B)C_in

where + is logical OR.

Based on this, in a multi-bit adder, each C_i can beexpressed in terms of the operand bits A_{i – 1} and B_{i – 1} as well as the carry C_{i – 1}. Using this relation, it is possible to express C_i as a function of the inputs to stages 0 to i – 1, so all the carries can be generated simultaneously. You will need more gates to implement it.)