(Solved): A microstrip line connecting two chips carries a 100MHz digital clocking signal which is, ideally, ...

A microstrip line connecting two chips carries a $$100\mathrm{MHz}$$ digital clocking signal which is, ideally, a square wave. The source-side chip is matched to the transmission line, while the load-side chip is unmatched with parasitic capacitance. This system can be modeled as the following circuit: We know from signal analysis that the square wave pulse train can be represented as a Fourier Series - a superposition of harmonic cosines. The first 4 non-zero frequencies for this particular clocking signal is $$0,100,300$$, and $$500\mathrm{MHz}$$. Calculate the steady-state impedance of the transmission line, $$Z_{in}$$, as seen from the source side for these 4 frequencies.