(Solved): A computer system's largest number of memory references, is made by the following LOAD instruction ...

A computer system's largest number of memory references, is made by the following LOAD instruction that performs a two-level memory indirect addressing : LOAD R1, [ [@DataPtr1] ] ] , in which: - R1 is a register, but DataPtr1, itself is a memory location. Each pair of square brackets represent a pointer derefrencing. - Once the value is retrieved, it is loaded into the \( \mathrm{R} 1 \) register. - The op-code for the LOAD can straddle two pages. Also each memory access in the operand can straddle two pages. What is the absolute minimum number of frames that should be allocated by this demand-paged system to a process to avoid thrashing? Hint: in addition to accessing DataPtr1 in the memory, there are two more memory accesses only to get the data value. 8 6 4 3 respectively are in the ready queue, in that order. What is the average Turn Around Time of the system, assuming that the context switch time is negligible? \( 30 \mathrm{~ms} \) \( 100 \mathrm{~ms} \) \( 50 \mathrm{~ms} \) \( 40 \mathrm{~ms} \) QUESTION 13 Assuming a \( 2 \mathrm{~KB} \) page size, what are the page numbers and offsets for the following address references (all numbers are in decimal): A) 5000 B) 136000 * All the answers are in (Page Number, Offset) pair format. A) \( (3,202) \), B) \( (65,830) \) A) \( (4,502) \), B) \( (66,832) \) A) \( (2,904) \), B) \( (66,832) \) A) \( (2,904) \), B) \( (67,704) \)