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(Solved): 1) The single cycle processor developed in the class is shown Figure 1. Suppose that the following ...



1) The single cycle processor developed in the class is shown Figure 1. Suppose that the
following instruction needs to be adSEX
&
?
16 Shift 32
Imm16.
RegDst
RegWr.
busW
32
20
Adder
10
Mu
Adder
Cik
Rd Rt
1 Mux Q
Imm16
Rs ,Rt
PC
T
Cik
32
32
Instructi

1) The single cycle processor developed in the class is shown Figure 1. Suppose that the following instruction needs to be added to our single-cycle datapath. bgezal rs, imm Opcode rs rt=0 Imm If (R[rs] ? 0) PC PC + 4+ (SignExt (Imm16) || 00) R[31] PC + 4 PC - PC+4 a) Remember that the original datapath in Figure 1 supports R-type instructions, orl (or immediate), lw (load word), sw (store word), and beq (branch on equal) and ALU implements and (logical and), or (logical or), add (addition), sub (subraction), and sit (set on less than) operations. Describe and sketch modifications needed to the datapath for bgezal instruction. Try to add as little hardware as possible. (10 points) b) For bgezal, give the values of all control signals including those you added in the first part. The number of grids below is not an indication of the number of control signals you will need. (15 points) Control Line 0/1/x Control Line. 0/1/x Branch ALUSrc RegDst ALUctr RegWr MemWr ExtOp MemtoReg Else SEX & ? 16 Shift 32 Imm16. RegDst RegWr. busW 32 20 Adder 10 Mu Adder Cik Rd Rt 1 Mux Q Imm16 Rs ,Rt PC T Cik 32 32 Instruction Memory Address Branch Mu ALUctr ALU Rw Ra Rb Register File WrEn Adr EXT Data 32 16 Cik Memory ExtOp ALU Src Figure 1. The single cycle datapath designed in the class. Rs Rt Rd Imm16 32, Equal MemWr 32 MemtoReg 0 Mu 32


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Instruction: add $1, $2, $3 Control signal Branch = 0 (This is not a branch instruction) RegDst = 1 (Destination register is
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