(Solved): 1. Sketch a transistor-level schematic of the following logic functions. You may assume you have b ...

1. Sketch a transistor-level schematic of the following logic functions. You may assume you have both true and complementary versions of the inputs available a. \( \mathrm{Y}=[(\mathrm{AB}+\mathrm{BC}+\mathrm{CA}) \cdot \mathrm{ABC}] \) b. \( \mathrm{Y}=[\mathrm{AB}+\mathrm{BC} \bullet(\mathrm{A}+\mathrm{B}+\mathrm{C})] \)